1. Field of the Invention
The present invention relates to a ferroelectric memory device that stores data in a nonvolatile manner using a ferroelectric capacitor.
2. Description of the Related Art
Recently, a great deal of attention has been paid to a ferroelectric memory (FeRAM: Ferroelectric Random Access Memory), as one type of the semiconductor memories, which is a nonvolatile memory that uses a ferroelectric capacitor. The FeRAM, which is nonvolatile, can be rewritten an order of 1012 times, and the reading or writing time is about the same as that of the DRAM. Further, the FeRAM can be operated at a low voltage of 2.5 to 5V. Due to these remarkable advantages, it is expected that the FeRAM replaces the entire memory market in near future.
An example of the FeRAM is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-255483 filed by the inventor of the present invention. This FeRAM has such a structure in which both terminals of the ferro-electric capacitor are connected to the source and drain of the cell transistor to form a memory cell MC, and a plurality of such memory cells MC are connected in series to form a memory cell block. (This FeRAM will be called “a series connected TC unit type ferro-electric RAM” hereinafter.)
FIG. 7 is a diagram illustrating the layout of an example of the structure of the series connected TC unit type ferroelectric RAM. FIG. 8 is a diagram showing a cross section of the structure shown in FIG. 7 taken along the line VIII—VIII.
A gate electrode 32 is formed via a gate oxide 42 on a semiconductor substrate 30. The gate electrode 32 serves as a word line WL. A diffusion layer (AA: Active Area) 31 is provided on both sides of the gate electrode 32 in the semiconductor substrate 30, and the diffusion layer serves as source and drain electrodes of the cell transistor on both sides, respectively.
A ferroelectric capacitor is provided above the cell transistor, and the ferroelectric capacitor includes a lower electrode 33, a ferroelectric film 34 and an upper electrode 35. The lower electrode 33, ferroelectric film 34 and upper electrode 35 are laminated one on another in this order to form the ferroelectric capacitor. The lower electrode 33 and the diffusion layer 31 are connected to each other via an AA-LE contact 36.
The upper electrodes 35 of two ferromagnetic capacitors formed adjacent to each other in one direction are connected together by a metal 38. The metal 38 and the diffusion layer 31 are connected to each other via an AA-M contact 39. A bit line 40 is provided above the memory cell MC. An insulating oxide layer 41 is formed on the semiconductor substrate 30.
In the ferroelectric memory, which has the above-described structure, the AA-M contact 39 is formed between the upper electrodes 35 within the same memory cell block. Due to the AA-M contact 39 formed there, the extending directional area of the bit line 40 of the ferroelectric memory is increased.
Due to the above-described structure, the bit line 40 is extended and therefore the parasitic capacity of the bit line is increased. As the result of increasing the parasitic capacity of the bit line, the read signal amount of the bit line is decreased.